A recurrent problem which is also particularly difficult to resolve of fast parallel memory circuits is the noise induced by the switchings of the output buffers. The problem is as more severe as higher is the degree of parallelism of the memory array and as greater is the specific speed of the memory. The numerousness and fastness of transitions determine large sudden power absorptions which generate oscillatory phenomena through supply lines and these, in turn, may trigger "rebounds" in circuits particularly vulnerable to noise. Generally the circuit portions of a memory most sensitive to noise are those wherein the nodes are driven to intermediate potentials as compared with the logic levels VDD-GND, such as sense amplifiers, voltage reference systems, and TTL-compatible input circuits. According to a known architecture, the various circuital structures which form the memory interact continuously among each other, thus propagating down to an output any change which may have occurred at any point of a signal propagation chain. The consequence is that the access and data extraction time is prolonged in practice beyond the design limits and the output switchings are affected by rebounds relative to false readings.
A disturbance is more likely to manifest itself as more close to an output is the circuitry vulnerable to noise; i.e., to a shorter path "source of disturbance - output buffer" corresponds a more immediate reaction to noise and a higher probability of the occurrence of resonance phenomena between two circuit portions.
For these reasons, sense amplifiers and the respective reference systems are the circuit portions most responsible for noise-induced instability because they are practically connected directly to the output buffers.
Heretofore, different approaches have been followed for reducing the magnitude of primary disturbances caused by transitions occurring in output buffers:
(a) reduction of the size of buffers; PA1 (b) elimination of crowbar currents in the final push-pull stages of the buffers; PA1 (c) performing constant-current transitions in the output stages; and PA1 (d) delaying output buffer transitions. PA1 However, all these known approaches do not entirely solve the problem and/or introduce an additional delay.